When AMD Acquires Taalas, a Chinese Company Decides to Etch AI Models into Silicon

On August 6, AMD announced its acquisition of Taalas, a pioneer in AI inference chips.

The deal sends an unambiguous signal: the center of gravity in AI compute is shifting from training to inference, and the ultimate answer to inference may not lie in general-purpose GPUs, but in silicon tailor-made for the model itself.

Almost simultaneously, a Chinese company pursuing the same path emerged — Shanghai Sytrix Technology (Sytrix). This chip company, focused on Model Processing Units (MPUs), just completed its seed round, with the goal of building China's first ultra-fast AI inference chip to rival Taalas.

Sytrix, whose name derives from the phrase "in an instant, intelligence awakens across all things," encodes the company's technical ambition in those eight characters: enabling token generation in the blink of an eye, allowing AI intelligence to emerge naturally with every inference. Its English name fuses "Synthesis" and "Matrix," signifying the transformation of model parameter matrices into hardware capabilities.

From General-Purpose to Specialized

AMD's acquisition of Taalas is, at its core, a major endorsement of the specialized architecture route.

NVIDIA's $2 billion acquisition of Groq, OpenAI's large orders to Cerebras, Etched's rapidly climbing valuation, and Taalas's ability to deliver from model to chip in 60 days — specialized inference architectures are moving from fringe exploration to the competitive core of the industry.

Over the past two years, the scale and cost pressures of AI inference have amplified exponentially.

A single agent loop requires 10 to 100 inference requests, token price wars continue to drive costs down, and NVIDIA GPUs still command gross margins of 80%. For every dollar spent on compute, 80 cents flows to the chip vendor. As compute allocation gradually shifts from training-dominated to inference-dominated, the market desperately needs an architecture "born for inference."

In China, this need is even more acute. China's compute market is projected to reach 1.05 trillion yuan by 2026. DeepSeek, Qwen, Moonshot AI, and Zhipu AI — mainstream models with the largest deployment footprints in China — all operate here.

Sytrix's answer is "hardening": baking model architectures and parameters directly into the silicon, making the chip a natural extension of the model, thereby shattering the memory wall entirely. Through self-developed parameter matrix decomposition technology, the chip accommodates several times more model parameters than competing products in the same die area, achieving hundredfold improvements in token throughput while consuming far less power than current inference chips.

"AI is powerful, but most people don't feel it in their daily lives yet: it's slow, it's expensive, and it mainly serves high-value tasks like coding and industry research. For more people's high-frequency, essential use cases, the experience just isn't good," said Sytrix's founder. "What we're doing is simple: building chips born for models from day one, making every token generation happen in an instant, turning accessible AI into a basic service within everyone's reach."

Sytrix's core product is likewise the MPU (Model Processing Unit) — a fully hardened compute array targeting specific AI models. Unlike traditional chips that are delivered first and then adapted by customers, Sytrix plans to deeply collaborate with model vendors during the model design or post-training fine-tuning stage.

For model vendors, this means lower token costs.

Token Costs Down 100x, Energy Down 100x

In the same die area, Sytrix's MPU can hold more model parameters than Taalas's HC1. Compared to current AI inference solutions, token costs drop 100-fold, inference energy consumption drops 100-fold, and latency is driven to extremely low levels. When models iterate, mask sets can be reused, and mature delivery cycles are far shorter than full re-tapeout times.

The underlying technical logic parallels Taalas's: through self-developed parameter matrix decomposition and model-circuit co-design, NRE costs are dramatically reduced while preserving room for joint optimization with model vendors and cloud compute providers. The difference is that Sytrix was designed from the outset to target China's mainstream open-source model ecosystem, with chip design always evolving alongside model development.

The arrival of the inference era, validation of the specialized route, HBM supply chain dynamics, and domestic substitution trends are all converging to make this the best possible moment for MPU entry.

A Team Combining Research and Engineering Depth

AI chips represent a systemic competition spanning algorithms, architecture, circuit design, and engineering delivery. When products are compared head-to-head, it ultimately comes down to the team.

Sytrix's founding team is led by PhDs from Tsinghua University's Yao Class, Shanghai Jiao Tong University's ACM Class, Peking University, Zhejiang University, and Huazhong University of Science and Technology, with core members having complete tapeout experience across multiple chips.

The CEO previously worked at a leading technology company with extensive experience in chip and AI commercialization. The CTO holds a PhD from SJTU's ACM Class, is an ICPC gold medalist, and has achieved extreme PPA optimization and tapeout on multiple core chip implementations. The Chief Scientist comes from Tsinghua's Yao Class, specializing in AI algorithms and combinatorial circuit optimization, with 40+ publications in top international conferences and journals. The model lead holds a PhD from Peking University, directing large-model inference optimization and hardware formal verification, ensuring chips are model-adapted from the very first design stage. Both the chip front-end and back-end leads have 15+ years of R&D experience, covering CPU/GPU/ASIC SoC chips, with end-to-end delivery of 20+ chips and cumulative production volumes in the tens of millions, possessing full-flow delivery experience from system architecture to mass production.

This is a team that understands both transistor physics and model mathematics. In the AI chip arena, the ability to vertically integrate algorithms, architecture, and circuits often determines who can turn PowerPoint efficiency ratios into real silicon measurements.

This seed round will primarily fund R&D and tapeout of Sytrix's first MPU chip, as well as core team expansion. Sytrix plans to establish deep partnerships with leading model vendors and cloud compute providers, collaborating with model vendors during the design phase to deliver customized inference chips for specific scenarios.

"Our vision is to become a driving force in humanity's march toward an era of accessible AI," said Sytrix's founder. "When inference is fast enough and cheap enough, intelligence will be like water and electricity — always available, within everyone's reach."

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