Architecture Revolution, Act Two: China's RISC-V Corps Fires the Opening Salvo in an Ecosystem Upgrade Battle | Unity Ventures Share

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Based on open source, surpassing open source.

In early March, foreign media reported that China plans to issue its first-ever policy guidelines to promote the nationwide adoption of open-source RISC-V chips. The ongoing tariff standoff has only accelerated the shifting dynamics in the chip industry.

Under the dual pressures of tariffs and technology blockades, the strategic value of RISC-V chips has become even more pronounced. As an open-source instruction set architecture, RISC-V provides a critical technical foundation for domestic chips to achieve autonomy and control.

In the era of large language models, the market is also urgently demanding highly customized, scenario-specific computing solutions. RISC-V's open-source, extensible nature allows enterprises to achieve modular customization on top of an open ecosystem—making it a strong match for high-performance computing.

The high-performance processor platform developed by Unity Ventures portfolio company Wehecore (微核芯) was designed from the outset as a flexible, multi-domain adaptable technology platform, with rich application directions spanning humanoid robots to edge servers, industrial control to automotive electronics.

RISC-V is like a set of "universal building blocks" with infinite potential—when deeply integrated with specific applications, it unleashes astonishing innovative energy.

Recently, the RISC-V instruction set architecture has once again broken into the global semiconductor spotlight with force.

According to a March 4 Reuters report, China plans to issue its first-ever policy guidelines to promote the nationwide adoption of open-source RISC-V chips, accelerating the industrialization of RISC-V technology. Meanwhile, European high-performance computing (HPC) institutions and enterprises have jointly launched the DARE project, committing €240 million to develop AI chips and software for the RISC-V architecture.

After 15 years of development, RISC-V is reshaping the global semiconductor landscape at a staggering pace. From DAMO Academy's soon-to-be-delivered high-performance processor C930, to Nuclei System Technology's advances in AI and automotive electronics, to Wehecore's breakthroughs in high-performance server chips, RISC-V is leading a technological revolution. This revolution is manifested not only in leaps in performance but also in its open, liberated nature, offering unprecedented opportunities for countless innovators.

Why RISC-V for the Dimensional Upgrade War?

The industrial evolution of processor architectures has always followed the iron law of "scenarios driving technology." In the late 1970s, Intel built the computing foundation of the PC era with its x86 architecture, establishing a four-decade industrial base. At the dawn of the 21st century, amid the Mobile Internet wave, ARM pioneered a new epoch of mobile processors with its energy-efficiency-first architectural philosophy.

Yet while these two systems have long dominated the market, they have embedded a dual structural contradiction. At the industry level, instruction set standard monopolies have created an inverted ecosystem where "hardware defines software"—users must modify their requirements to fit the processor, leaving limited room for scenario-specific optimization. At the technical level, the demand for full-scenario coverage has generated massive cost redundancies such as power consumption overhead.

As computing paradigms enter a new stage dominated by cloud-native and AI large models, three breakthrough windows have opened for architectural innovation. Heterogeneous computing has created demand for dynamic collaboration between CPUs and AI accelerators, while the refinement of industry scenarios has forced architectural design granularity to improve by two to three orders of magnitude.

Against this backdrop, the RISC-V open instruction set demonstrates disruptive potential: its modular architecture supports agile customization ranging from AI inference units to domain-specific processors, while its open-source ecosystem breaks the four-decade standard monopoly over instruction set architectures.

Omdia predicts that from 2024 to 2030, RISC-V-based processor shipments will grow at nearly 50% annually, reaching 17 billion units by 2030 and capturing nearly a quarter of the global market.

Notably, China's semiconductor industry has demonstrated a unique strategic path in this architectural revolution. Beijing Wehecore Technology Co., Ltd. (hereinafter "Wehecore"), founded in 2020, stands as a representative example.

At that time, 90% of global RISC-V developers were focused on the low-end AIoT market, while this Chinese chip company presciently locked onto two high-end tracks—servers and AI computing—precisely the critical battlegrounds for breaking through overseas technology blockades and achieving architectural autonomy.

The Duet of Technical Accumulation and Innovative Breakthroughs

In the semiconductor industry, each generational architectural breakthrough requires decades of experience. The Wehecore team has condensed over twenty years of industrial know-how, successfully advancing from technological parity to leapfrogging. Its self-developed high-performance processor achieves a SPEC CPU2006 score of 15 points/GHz, matching the performance of ARM's latest server chip, the N2.

This team covers every aspect of high-performance processor development, including architecture design, verification, physical implementation, and software across the entire process. Thus, they are fully capable of providing a "full-stack" server system solution—high-performance CPU cores + Network-on-Chip (NoC) multi-core interconnect + SoC architecture—combined with Chiplet technology, significantly reducing chip design and manufacturing costs while accelerating R&D iteration.

Image source: Wehecore

Take the GKG series as an example. This high-performance RISC-V chip integrates multiple self-developed high-performance processor cores, employing out-of-order multi-issue superscalar pipelines. Building on the RISC-V base instruction set, it supports high-performance instruction set extensions including hardware virtualization, vector processing, and AI. With advantages in high performance and low power consumption, it has achieved large-scale commercial deployment in servers, terminal devices, embedded equipment, and industrial control—demonstrating the innovative potential of the RISC-V architecture in high-performance computing scenarios.

Image source: Wehecore

In Wehecore's view, behind these achievements lies the continuous evolution of two core capabilities:

The first is "global optimization" capability: the unique ability to coordinate architecture design with process evolution, maintaining autonomous control from chip architecture design through process implementation. This enables superior power efficiency and stronger performance while significantly shortening development cycles.

The second is "tailor-made" capability: customizing chip architectures according to specific customer needs, uniformly optimizing and decomposing task metrics at each stage, and through rational resource scheduling, fully leveraging process performance to ensure the processor's competitive edge.

As a result, Wehecore has established a technical moat in just a few years, having filed for over 70 Chinese invention patents and secured multiple core patent authorizations in Europe and elsewhere.

Image source: Wehecore

Leveraging its deep technical accumulation, Wehecore has also continuously refined its customization services, launching the RISC-V High-Performance Processor Customization Platform. This platform encompasses RISC-V high-performance processor cores, Network-on-Chip (NoC) multi-core interconnect, SoC architecture, and software platforms, providing users with comprehensive, unified hardware-software optimized chip solutions. The critical high-performance processor cores, NoC multi-core interconnect, and SoC architecture are all self-developed, supporting customization at multiple performance levels with deep optimization based on user requirements.

The RISC-V high-performance platform spans a wide range of applications, including data center servers, robotics, autonomous driving, and high-density computing clusters.

Breaching the Technical No-Man's-Land of x86/ARM

As waves of technological innovation push toward industrialization heights, Wehecore has adopted a strategy of deep integration with applications—aiming to do "what x86 and ARM want to do but cannot."

The core challenges for current RISC-V architecture to achieve large-scale commercialization focus on two dimensions, with breakthrough paths systematically presented as: an ecosystem trust-building project and a differentiated track precision breakthrough strategy.

Specifically, ecosystem confidence can be built through policy coordination mechanisms, technical validation loops, and industrial collaboration networks. Differentiated track breakthroughs can target computing reconstruction opportunities, emerging domain positioning, and demand-driven development.

This is the commercialization path Wehecore has continuously explored: building a three-dimensional ecosystem system guided by policy, led by enterprises, and supported by academic institutions, forming breakthrough momentum in trillion-dollar markets such as intelligent computing, automotive electronics, and industrial automation. The core element lies in precisely identifying the rigid demand gaps in x86 and ARM architectures, transforming RISC-V's architectural freedom into scenario adaptation advantages, and ultimately achieving closed-loop transformation from technical advantage to commercial value.

Triggering a Tsunami in the Deep Waters of AI Computing

Today, as AI technology sweeps the globe with accelerating algorithmic breakthroughs and deep penetration into core business applications, how to build a systematic strategic framework for the AI era has become a critical proposition in corporate strategic planning.

In the evolution map of general-purpose technologies, RISC-V and AI technologies share significant common characteristics—both represent bottom-level architectural innovations whose true value release requires deep integration with vertical scenarios. Facing the generational gap in advanced processes and ecosystem chains in China's semiconductor industry, Wehecore has chosen to focus on scenario-driven architectural innovation.

Take the humanoid robot domain as an example. Its technical requirements matrix comprises three core dimensions: energy efficiency constraints, real-time multimodal interaction, and cognitive intelligence realization. Existing general-purpose computing architectures struggle to meet such composite technical indicators—precisely the opportunity window for synergistic innovation between the RISC-V open instruction set and AI acceleration architectures.

Image source: Wehecore

AI chip development requires balancing general-purpose and specialized capabilities through rational optimization based on application needs. Wehecore identifies a fundamental disconnect in traditional architectures: CPUs execute control flows, while AI (or GPGPUs) execute data flows; yet in real applications, there are no absolute data flows or absolute control flows—rather, there are combinations of the two with different ratios for different domains.

Task decomposition and scheduling are key to determining chip system solutions, requiring deep binding between applications and chip design. Thus, designing a CPU-AI collaboration framework is essential. Meanwhile, hardware-software collaborative frameworks are particularly important, requiring deep decomposition of applications, computing frameworks, data flows, and control flows from the application perspective.

Wehecore has proposed a three-level CPU+AI collaboration framework:

Solution 1: Integration of AI acceleration modules within an SoC framework;

Solution 2: AI instruction extensions at the CPU level;

Solution 3: AI coprocessor design within the CPU framework.

In the current market, most chip solutions adopt Solutions 1 and 2. Solution 1 offers high AI execution efficiency but poor adaptability to future applications, with weak integration with control flows and interaction with the CPU limited to the memory level. Solution 2 offers optimal application adaptability but the lowest AI execution efficiency, confined to special application domains where control flow dominates and data flow is secondary.

Solution 3 is based on a high-performance CPU framework, preserving the strong control flow execution capabilities of high-performance CPUs while combining the high AI execution efficiency advantages of an AI coprocessor. Wehecore believes this represents the future development trend for AI chips.

Academician Ni Guangnan of the Chinese Academy of Engineering foresees that the RISC-V architectural revolution has arrived. In this campaign to redraw the global computing map, Wehecore is forging a new RISC-V core with Chinese ingenuity.

Source: Chip Master